The present invention relates to a semiconductor device and a fabrication method for the same, and more particularly, to a semiconductor device having two types of especially miniaturized transistors and a fabrication method for the same.
In recent years, there have been requests for semiconductor devices with lower power and higher-speed operation. For speedup of semiconductor devices, known is a method in which the gate capacitance of a metal insulator semiconductor field effect transistor (MISFET) is increased to increase the drive current.
To increase the gate capacitance, a gate insulating film must be thinned to shorten the inter-electrode distance (distance between a substrate and a gate electrode). At present, the physical thickness of the gate insulating film of a MISFET has been reduced to as small as about 2 nm when silicon oxide nitride (SiON) is used.
With the thinning of the gate insulating film, increase in gate leak has increasingly become a problem to be addressed. To reduce the gate leak, use of a material high in dielectric constant such as hafnium (Hf) oxide, in place of a conventionally used silicon oxide (SiO2) series material, as the gate insulating film has been examined.
The thinning of the gate insulating film also causes a problem that with the hitherto used gate electrode made of polysilicon, the gate capacitance decreases due to depletion of the gate electrode. The decrease of the gate capacitance is equivalent to increase by about 0.5 nm of the thickness of the gate oxide film made of SiO2, for example. The thinning of the gate insulating film inevitably involves increase in gate leak. However, if only the depletion can be suppressed, the effective thickness of the gate insulating film can be reduced with no increase in gate leak. In the case of SiO2, when the thickness is reduced by 0.1 nm, the leak current will be ten or more times as large as that before the thinning. In this case, therefore, the effect of suppressing the depletion of the gate electrode will be great.
To avoid depletion of the gate electrode, examination has been made on replacing the material of the gate electrode from polysilicon to a metal free from causing depletion. However, while it is possible to form electrodes for p-MISFETs and electrodes for n-MISFETs differentially with polysilicon by forming an impurity level with implantation of an impurity, such differential formation is not available with metal.
In the present semiconductor devices, reduction in threshold voltage (Vt) is indispensable to respond to the request for higher-speed operation. For lower Vt, electrodes for p-MISFETs and electrodes for n-MISFETs must have work function (WF) values close to the band edges of silicon. While a high WF close to the WF value (about 5.2 eV) at the top (top edge) of the valence band of silicon is required for electrodes for p-MISFETs, a low WF close to the WF value (about 4.1 eV) at the bottom (bottom edge) of the conduction band of silicon is required for electrodes for n-MISFETs.
Since there is no ideal metal material responding to the above request, examination has been made on use of a metal having a WF value corresponding to roughly the center between the WF value of the p-side region and the WF value of the n-side region. With this, a p-MISFET and an n-MISFET can be made to have the same Vt value. However, as the request for lower Vt progresses, such a semiconductor device is becoming no more practical.
At present, searches have been vigorously made for metal materials usable as electrodes for p-MISFETs and n-MISFETs, and recently some promising candidates have been found. Promising candidates for n-MISFET electrodes include Ta series electrodes such as TaC and TaN in combination with a gate insulating film (including the case of a cap of a gate insulating film) including a lanthanoid series material such as La. Promising candidates for p-MISFET electrodes include precious metals such as Pt and Ir, MoO, and the like.
In actual application of the above metal materials to transistors, use of a metal inserted poly-Si (MIPS) structure has been examined from the standpoints of consistency with the conventional processes and microfabrication. The MIPS structure is a multilayer structure of a metal material having a thickness of about 10 nm or less and polysilicon having a thickness of about 100 nm or less deposited on the metal material.
A complicate process must be passed for fabricating a semiconductor device like a complementary metal insulator semiconductor (CMIS) having a p-MISFET and an n-MISFET whose gate electrodes are different in material or composition formed on the same semiconductor substrate. For example, a metal for the n-MISFET is deposited on a gate insulating film, the portion of the metal for the n-MISFET formed in the p-MISFET region is selectively removed, and a metal for the p-MISFET is deposited on the portion of the gate insulating film in the p-MISFET region (see F. Ootsuka, et al., “extended abstract of the 2006 international conference on solid state device and materials, Yokohama,” 2006, pp. 1116-1117 (Non-Patent Document 1), for example).
The above process not only increases the number of process steps, but also causes a non-negligible increase in misalignment because two times of lithography are necessary for removal of the portion of the p-MISFET metal deposited in the n-MISFET region and for removal of the portion of the n-MISFET metal deposited in the p-MISFET region.
If the metal for the p-MISFET and the metal for the n-MISFET overlap each other at the boundary between the p-MISFET region and the n-MISFET region, a metal remainder will be formed at gate etching. For this reason, it is not allowed to form the metal for the p-MISFET and the metal for the n-MISFET continuously. At present, the required minimum width of the element isolation region (STI) is 100 nm or less. If the minimum width of the element isolation region becomes smaller, it will be substantially difficult to secure an alignment margin with which the metal for the p-MISFET and the metal for the n-MISFET will never be in contact with each other and the interface of the metals will never be shifted to enter an element formation region from the element isolation region. Also, etching of the element isolation region that may occur during each etching process step will cause a serious problem.
For simplifying the process, an attempt has been made to form the gate electrode of a p-MISFET and the gate electrode of an n-MISFET of a same metal material. In this method, in either the p-MISFET or the n-MISFET, a cap film having a thickness of about 1 nm may be inserted between the gate insulating film and the gate electrode, to obtain optimum effective work functions (eWF) required for the p-MISFET and the n-MISFET. Examination has also been made to use different cap films for the p-MISFET and the n-MISFET (see N. Mise et al., IEDM 2007, pp. 527-530 (Non-Patent Document 2), for example). In this structure, in which the gate electrode of the p-MISFET and the gate electrode of the n-MISFET are made of a same material, working such as gate etching is greatly simplified.